View condensed White Paper  Keeping pace with technology How synchronous memory will impact top-level IS planning A VisionTek White Paper By John Wagner A paradigm shift is occurring in the memory industry. Once considered a stable environment, memory designs are now dynamic and drive system performance. Contents I. Introduction II. DRAM 101 III. Development and implementation of the new technologies
IV. The future: Rambus
vs. DDR and SynchLink
For almost 10 years, DRAM architecture has remained stable, and memory upgrades easy to implement, with the most significant changes occurring in the speed and addressing used by devices demanding access to the system RAM. For many IS professionals, memory wasn’t something they needed to spend much time thinking about. All this, however, is about to change. Changing market conditions, changing technologies and a major paradigm shift in the memory industry will enable systems to reach new levels of performance and efficiency. The benefits will come at some cost, however, requiring judicious on-going planning and management to cost-effectively maximize the performance boost. Synchronous DRAM, introduced earlier this year, is the first real shift in core memory design since the late 1980s. The performance criteria for SDRAM, while only subtly different from today’s asynchronous standard DRAM, will make a world of difference in how memory is viewed in overall system performance and technology lifecycle management. The asynchronous nature of DRAM used in electronics applications and PC architectures during the past decade allowed an autonomous implementation of memory solutions. These asynchronous DRAM architectures have 3 primary operations (read, write, and refresh) and primarily provide data storage solutions. While SDRAM (synchronous DRAM) is fundamentally similar in operation to asynchronous DRAM, SDRAM differs in its clocked interface and multiple bank architecture support. Definitions: Today, consumers expect their systems to nimbly handle all types of streamed data, such as Internet applications and multi-media applications which incorporate 3D audio and video. Bus traffic flows across the PCI bus between DRAM, SCSI devices, IDE, ISA, USB and soon Firewire-based peripherals. These data streams include network traffic, video, and high-fidelity audio inputs from digital-video disk (DVD) and hard disk subsystems. For the last decade the CPU has been the driving element in overall system performance. Today, as we move to specialized subsystems, a balanced system will determine the ultimate system performance. As new systems emerge and CPUs are packed with ever-greater resources (super-pipelined, superscalar, with multiple execution units, branch prediction and speculative execution techniques), Intel and other semiconductor companies have been concerned that the steady stream of instructions from memory to the processor may not be able to keep pace. Multiple resource demands on the CPU mean a single cache miss can domino into the halt of several instructions and cause unstable delivery of streamed data. In addition, new engines such as graphics accelerators, I/O servers and multimedia processors live on the same system bus as the SDRAM and each can concurrently demand direct access to the memory. Synchronous DRAM provides the performance necessary to handle these tasks, alleviating the concerns of CPU manufacturers, and will become a driving force leading computing devices to a new level of functionality. Added performance = added complexity The added complexity of numerous, increasingly sophisticated board-level subsystems all timed on the same clock, however, requires module designers to develop a larger portfolio of systems specific modules, reducing the overall generic applicability of any give module design. At 100MHz, the problem intensifies, influencing the actual architecture of the modules. All of these changes boil down to a significantly more complex system configuration puzzle. Memory management takes on greater importance in the overall picture. As system speeds increase, the tolerance between a working module and a disaster waiting to happen narrows, placing a greater burden on the buyer to ensure compatibility with the host system. Inventory of memory will also become more complex since one module will no longer be suitable for more than one system model in place. Compounding this complexity is an often-confounding array of potential new memory choices vying for supremacy as the next-generation memory solution. We hope the following white paper, which begins with a DRAM primer and provides detailed information on SDRAM and its roadmap for the future provides a valuable addition to your understanding of the changing memory industry and the impact it will have on IS planning.
A DRAM is a block of memory cells arranged in rows and columns, with logic that controls the ability to read and write data into each of the cell locations. Additional logic is present to "refresh" the data in order to keep the integrity of the stored data. This refresh is necessary because each cell is basically a capacitor. Capacitors store bit-level information (a 1 or a 0) for short periods of time when charged. As capacitors are not batteries, and cannot maintain a charged state (they deplete power over a specified time period), it is necessary for the cells to be refreshed to maintain the data. Today, there are several types of memory available, nearly all are based on traditional DRAM: - Synchronous DRAM (SDRAM) - Rambus DRAM (RDRAM) - Three-dimensional DRAM (3D RAM) - Extended data out DRAM (EDO) - Hyper page-mode DRAM - Video DRAM (VRAM) - Synchronous Graphics DRAM (SGRAM) - Cache DRAM (CDRAM) - Enhanced DRAM (EDRAM) - Multibank DRAM (MDRAM) While every generation of DRAM density has increased four-fold, only recently has there been an emphasis on truly improving speed. Microprocessor speeds have outpaced memory to the point where caches just aren't fast enough. Main memory, in the form of DRAM, now has to do its share with meeting these demands. Partly due to performance levels now being achieved by the CPU, the memory subsystem architecture would become a performance bottleneck if an asynchronous approach were maintained. In addition to advances in the host processor, new "engines" (i.e. graphics accelerators, I/O servers and multimedia processors) are being added to supplement overall system performance. Each of these devices too, lives on the same system bus as the SDRAM and each can directly demand concurrent access to the memory. Despite the differences between DRAMs, all have attempted to provide higher performance and higher bandwidth. With the increase in DRAM densities, the fundamental conflict is between providing higher performance and providing a reasonably minimal amount of memory sizes. Fast Page Mode (FPM) memory is the oldest option currently in use in electronic devices or PCs. This read technique was the first to implement the ability to read a complete "page" of data - in which all of the memory cells have a common row address - during a single access cycle. The new DRAM types developed to supercede FPM can be categorized in three basic groups: conventional, evolutionary, and revolutionary. Conventional choices entail relatively minor changes to the generic DRAM interface. Evolutionary architectures offer more bandwidth than ordinary DRAMs, yet rely on the same separate bus and multiplexed address bus as conventional DRAM. Revolutionary DRAM choices are complete redesigns of the interface. This redesign is intended to provide a higher bandwidth and a fewer number of module sizes. The three leaders in each category are: EDO as the conventional DRAM, SDRAM as the evolutionary, and Rambus as a revolutionary. Extended Data Output (EDO) takes the technique used in FPM designs and makes an improvement in staging the data, thus reducing the time required to read multiple cycles. EDO performance is improved by holding data longer during recovery times, and reducing page-read cycle times to 25ns from 40ns. EDO is considered the last hurrah for fast-page devices. This architecture took over as the primary memory of choice in 1995 simply because of the extra performance it offered with little or no additional cost for the design change. As memory bus speeds move beyond the 40MHz range, EDO will lose mainstream viability to SDRAM. Synchronous DRAM is an alternative to VRAM at a lower cost. The real key to SDRAM is its dual bank interleaved architecture. By using two banks, the memory can switch back and forth, essentially doubling the IC’s rate of speed. The difficulty with this approach is that twice the memory is required. SDRAM simplifies the situation by interleaving two memory arrays into a single device. Today, Rambus is considered a good solution for contained (1-2MB) applications such as graphics boards simply because the frequency is higher than can be sustained across the entire system board. Rambus is not yet being used for broader applications, however it is also one of the major contenders to replace SDRAM as the main system memory during the first years of the new millenium (see section IV). Asynchronous vs. synchronous: A graphic illustration The following illustrations may appear complex, but should be helpful in trying to understand the differences between current asynchronous architectures and SDRAM. Note the asynchronous 40ns cycle timing; this will be an important point of comparison when looking at the timing chart for synchronous architectures. |
| Asynchronous (legacy designs)
Synchronous (High performance next generation)
|
Memory technology
– bus speed match-up Figure 4 |
| Direct RDRAM The Rambus DRAM (RDRAM) evolved from research in the late 1980s on how to cost-effectively maximize performance of generic DRAM. RDRAMs interface with the Rambus memory controller in a packet-based fashion. Base and concurrent RDRAMs transfer address, data, and control information across the Rambus channel via a common set of eight or nine pins that are synchronized with the clock by careful impedance and trace-length matching. The Rambus-controller design includes a demultiplexer to convert the high-speed, 8- or 9-bit channel back to its 64- or 72-bit lower frequency alternative within the system controller. Reliable RDRAM operation requires careful printed circuit board layout, especially in multi-chip designs, to keep the total channel length as short as possible and to eliminate differences in trace length and impedance between signals. Achieving this goal ensures that signal-to-signal skew is as small as possible. The maximum number of chips per Rambus channel is 32. This restriction is one of the key Rambus-architecture concerns for high-end servers and workstations, although this can be overcome by adding channels to the memory controller, or by providing a channel-to-channel bridge chip. The close chip-to-chip placement, combined with frequency-driven high dynamic-power consumption, also creates thermal-dissipation challenges that did not exist with previous generation SIMMs and DIMMs. SLDRAM-architecture definition efforts, which had been slowly progressing for several years, accelerated early this year in response to the Intel/Rambus announcement at the International Solid State Circuits Conference in February. SLDRAM developed from two previous IEEE high-speed bus standards: the 1595 Scalable Coherent Interface (SCI) and the 1596.4 RamLink, an SCI subset that removed multiprocessor and other features that the IEEE committee judged unnecessary for the target applications. SLDRAM further modified the point-to-point RamLink interface by optimizing for multi-chip DRAM arrays, a maximum 64-byte burst length for high-end CPU cache-line fills, and a 3-to-1 average read/write-access ratio. Because Direct RDRAM and SLDRAM are similar, at least at a high level, many of Direct RDRAM's strengths and shortcomings apply equally to SLDRAM (see Figure 5 and Figure 6). One difference between the two competing approaches involves the output-buffer structure. RDRAM uses an open-drain output with pull-up resistor termination at the end of the Rambus channel. SLDRAM will use a push-pull, low-voltage-swing, full-CMOS output that is conceptually similar to SSTL. SLDRAM-bus termination will consist of pull-up resistors plus series-stub resistors on each memory module. Almost every DRAM manufacturer participates in the SLDRAM Consortium, to one degree or another. Some contribute only money and a meeting representative, whereas others dedicate small engineering teams to the effort. Hyundai and Mitsubishi are creating an SLDRAM conceptual test chip due for completion late this year, consisting primarily of I/O drivers and current-, voltage-, and timing-adjustment circuits. IBM Microelectronics is developing a companion evaluation module and system-board design. Samsung proposed DDR to JEDEC in December 1996, and several DDR standards are nearing approval. Many memory suppliers are considering supporting DDR beginning at the 64-Mbit density. Samsung is preparing for DDR production in mid-1998. Some companies, in fact, hope to design standard and DDR SDRAMs on the same silicon to minimize risk and improve demand flexibility. DDR supporters claim the bandwidth capacity is near 200MHz, and only limited by address- and control-cycle overhead and the fact that address cycles will use only the rising edge of the memory clock, giving them half the bandwidth of data cycles. For this reason, most DRAM manufacturers planning to offer DDR will bypass the 66/133MHz option and go directly to the 100/200MHz version. Because DDR is conceptually so similar to standard SDRAM, it uses much of SDRAM's test, assembly, and board- and module-manufacturing infrastructure. DDR is also an open architecture that promises to be a simple transition for both memory and chip-set manufacturers. However, Intel states that it plans no support of DDR in any upcoming chip sets. Even without Intel's involvement, which may change in the future, DDR may find sufficient interest to ensure at least some market success. As discussed, the memory industry is in a time of major transition, moving from not only 32-bit 72-pin SIMMs to 64-bit 168-pin DIMMs, but also from asynchronous SIMMs to synchronous DIMMs. The 72-pin SIMM configuration was relatively simple partly due the amount of tolerance allowed each design. SIMM choices were 5V, non-parity/parity/ECC, FPM/EDO, with different present detect configurations. 168-pin DIMMs, on the other hand, are more complex as there are more variables involved in the module design. DIMM choices are non-parity/parity/ECC, 5V/3.3V, FPM/EDO/SDRAM, buffered/non-buffered, SPD (Serial Present Detect), registered or non-registered. As the process for memory enhancement becomes more refined (or complex depending on the viewpoint), the investment required to correctly identify modules for any given platform continues to increase. Managing memory implementation and upgrades will also require a greater investment in time and planning. The best philosophy is to be consistent in supplier selection and aggressively configure systems to avoid constant interim enhancements. Most importantly demand quality memory products and suppliers who stand behind their products with a depth of engineering and in-house design resources. Taking the time to plan ahead for this on-going management will be a key factor in making the most of your IT investments. Following are more details and suggestions on effectively managing the changeover to SDRAM to maximize its performance-boosting potential. Focused System Upgrades The importance of module selection will increase for IS departments as modules become more specific to a host platform and will not be as interchangeable. Vendors who, up until now, have been supplying SIMMs to a fairly generic market, may be excluded from the memory market due to the complexity of synchronous design and manufacturing. Limit the number of changes With Intel delivering 32-bit (soon 64-bit) processors into the next decade, SDRAM and Rambus running to 300MHz and beyond, IEEE-1394 providing up to 400Mbps I/O, and AGP video acceleration, a total performance improvement of 10 times existing platform capacity will be possible. Balance is the key to true system throughput, and becomes increasingly important as we exercise higher frequency architectures. Develop a roadmap and system strategy During this evolutionary change in the memory market, it is critical for an enterprise to have an implementation strategy. Knowing which platforms are upgradable and where they are on the depreciation curve is a fundamental requirement for next generation enterprises. Correctly linking a platform to a function, and knowing when that system has exceeded its effectiveness in that function, will provide the opportunity for a planned enhancement and help eliminate roll-out risk. A strategy for configuration "adjustment" provides the ability to:
Stick with known-good-partners The memory technology paradigm shift places a much greater quality and testing burden on memory module makers than ever before. Module manufacturers’ investment in the necessary equipment to support the development, manufacturing and testing of the new modules-types is a critical issue for the more-complex SDRAM. Because of the significant expense involved in producing quality SDRAM, it will become more important than ever the carefully quality memory vendors. Most importantly, demand quality, and a supplier who stands behind their prodcts and can provide the following:
The VisionTek advantage VisionTek has always extended its quality commitment to the development and implementation of new technologies. One of the nation’s leading suppliers of memory upgrades and valued-added peripherals, VisionTek is on the forefront of SDRAM module design. We are making all necessary investments in test equipment to support the design and manufacture of these more-complex modules. VisionTek offers a full line of memory upgrades, including SDRAM modules. We also design and manufacture system memory for leading computer OEMs (original equipment manufacturers). All VisionTek memory is guaranteed compatible, warranted for life and backed by lifetime, free technical support. Our quality measures are guaranteed to be consistent by our ISO 9001 certification – the highest quality standard available for design and manufacturing. Through our extensive field sales force, VisionTek will assist corporate end-users with upgrade project assessment and management - helping you cost-effectively maximize your performance potential with a current system upgrade or a transition to SDRAM-based systems. Our mission is to help you extend the life and maximize the performance of your technology investments. For more information, please browse our web site at www.visiontek.com, or call us at 1.800.726.9695. References
Edited by Cynthia Kater, Marketing Communications Manager, VisionTek |
Please mail your Web site comments to webmaster@visiontek.com |
This page last updated on June 28, 1998.
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